A single microengine per Gigabit port is responsible for receiving and buffering packets in . All remaining microengines execute application-specific filter expressions. For this purpose, we implemented an FPL-2 compiler that generates Intel's microengine-C. On each of the microengines a skeleton main loop with a slot for user code is provided by the FFPF framework. Users with the right credentials may `plug in' FPL-2 expressions in this slot. When such a flow grabber is instantiated, the complete program is loaded on the microengine.
An FFPF IXP1200 filter is bound to a microengine's filter. As a consequence, the IXP1200 can support a maximum of five filters. As the IXP1200 is considered `obsolete' and no longer supported by Intel, and newer versions of the IXP support more microengines at higher clockrates, both the number of filters that can be supported and their speeds may be expected to increase.
A filter uses all four threads to process the packets one by one. If
the filter determines that the packet is interesting, the microengine places an index for the packet in the filter's
. Otherwise, a
pkt_drop() marks the packet as finished by
setting a flag in the SRAM packet descriptor entry. In addition, it
checks if all other filters are also finished with the packet. If so,
the packet descriptor will be reclaimed.