Powerful embedded processors form the core of many modern consumer electronics (CE) devices. They perform the various signal processing tasks required for audio, video, and transmission handling. Often these processor cores consist of DSPs (Digital Signal Processors) or custom designed VLSI cores.
There are a number of problems industry is facing that need attention. A major problem with CE devices is that, due to the increased density in VLSI chips, design and layout of electronic circuits containing various processing components is taking too much time with respect to the ever shortening time-to-market demands of manufacturers of CE devices. Inferior programming methodologies that are currently used for CE devices are making the problem even worse. Application programming is still done by writing hand tuned sequential code in languages like C or even in assembler. Consequently, software design time is high and portability is low, thus increasing time-to-market. A major scientific challenge (with high industrial impact) therefore is how to develop an architecture and programming methodology that reduces the total system development time. The SPACECAKE architecture designed by Philips addresses the architectural part of this problem. It is based on the idea of tiles. A tile is a heterogeneous multiprocessor with a shared memory architecture. A SPACECAKE system consists of a regular structure of tiles.
An open problem, however, is how to develop efficient applications for these types of architectures. Programming a SpaceCake system intrinsically means the use of parallelism. In the SCALP project, we will investigate whether a suitable and effective parallel programming paradigm can be defined that is scalable, portable, and predictable. We will base our parallel programming model on SP (series-parallel) graphs, which offer significant advantages with regard to the ease of programming, portability, and performance predictability. We will explore whether SP design patterns can be defined for a relevant set of current and future CE-applications. These SP design patterns will be embedded in an SP programming environment that also provides accurate, low cost estimations on the performance of the design patterns.