next up previous
Next: FFPF on the IXP1200 Up: The IXP1200 packet source Previous: The IXP1200 packet source

The IXP1200 processor

The Intel IXP1200 runs at a clockrate of 232 MHz and is mounted on a Radisys ENP2506 board together with 8 MB of SRAM and 256 MB of SDRAM. The board contains two Gigabit network ports \vbox{\kern3pt\textcircled{{\scriptsize{1}}}}. Packet reception and packet transmission over these ports is handled by the code on the IXP1200 processor \vbox{\kern3pt\textcircled{{\scriptsize{2}}}}. The Radisys board is connected to a Linux PC via a PCI bus \vbox{\kern3pt\textcircled{{\scriptsize{3}}}}. The IXP itself consists of a StrongARM host processor running embedded Linux and six independent RISC processors, known as microengines. Each microengine has its own instruction store and register sets. On each of the microengines, registers are partitioned between 4 hardware contexts or `threads' that have their own program counters and allow for zero-cycle context switches.

Figure 10: The IXP1200 NPU

Herbert Bos 2004-10-06